Aurora is an open standard link-layer protocol invented by Xilinx for serial connectivity and data transmission. Features include general purpose data channels with 622 Mb/s to over 100 Gb/s of data throughput, full duplex or simplex operation, flexible framing with unlimited frame sizes, flow control, and automatic initialization and channel maintenance.

Aurora automatically initializes a channel when connected to an Aurora channel partner. After initialization, applications can pass data across the channel as frames or streams of data.

Substantial benefits of Aurora include it’s low latency, low overhead protocol, minimal logic resource utilization, and consequent simplicity. These attributes make Aurora an excellent on-board chip-to-chip protocol for serial links. An example could be transmitting data from an A/D or custom fibre mezzanine to another FPGA on a carrier board. In this implementation, data is often streaming on a dedicated path, possibly in a single direction. There is no need for the features of a more robust protocol, and the overhead, latency, logic utilization and complexity associated with such a protocol. It provides the ability to easily avail of serial Multi-Gigabit Transceivers (MGTs) such as the Xilinx RocketIO SerDes, enabling the use of a high speed serial interconnect where the implementation difficulties associated with a more robust interconnect such as Serial RapidIO, PCI-Express, etc. would be in excess of application requirements.

Embedded System Backplanes: Where Aurora falls short

Today’s embedded system backplanes require running at multi-gigahertz speeds to meet application performance requirements. Utilizing parallel signaling to achieve such performance requirements is not desirable or likely possible with any degree of reliability. As such, practically speaking, active backplanes need to be replaced with serial backplanes to meet next generation performance and signal integrity requirements.

Just as such next-gen backplanes require high speed, passive serial connectivity, they generally require point-to-point switch fabric connectivity. This has been observed with the popularity of ancillary interconnects as RACEway on VME, where point-to-point switch fabric connectivity enabled different boards to simultaneously communicate with one another. Even in the desktop PC and server markets, the requirement for switch fabrics has been acknowledged and realized by PCI-Express.

Switch fabrics require, among other things, infrastructure such as multi-port crossbar switches. These switches are generally off-the-shelf ASSPs (ASIC-Specific Standard Products), and can be found for any major industry fabric such as Serial RapidIO, PCI-Express, Infiniband, Ethernet, etc. These devices are major undertakings and due to various resource requirements in terms of logic and internal clock frequencies, often require an ASIC implementation. No such device for Aurora exists as it is, of now, an FPGA centric protocol.

But another critical part of the infrastructure that makes readily utilizing these crossbar switches practical in an embedded system is the protocol itself. This is where Aurora is inherently lacking, and the same reason that it is attractive for chip-to-chip interconnects that do not require a robust networking protocol.

While Aurora is an excellent lightweight protocol for serial connectivity between on-board devices, particularly from devices on mezzanines to devices on carrier boards, it was not originally intended to support full mesh switch fabrics and is essentially a Xilinx, vendor-driven specific protocol for use in FPGA-to-FPGA communications. As such, it is not an optimal solution for which to base an embedded system backplane. In today’s embedded systems, payload boards or blades generally have present or future requirements for simultaneous point-to-point communications only possible with a switch fabric. And such systems can not be limited by the requirement that every board in the system interface to the backplane through an on-board Xilinx FPGA.