Primary Multi-Port DDR Controller
Memory controllers are one of the most critical functional blocks to an optimally designed System-on-Chip.  The Multi-Ported DDR Controller serves as CoSine’s Primary memory controller and fully leverages Micro Memory’s specialized knowledge and expertise in this core area of digital design.

Although CoSine has multiple high speed internal data buses between logical blocks, bridging through large multi-ported memory controllers is the highest performance solution for transferring data between different bus protocols in real time.

Instead of relying on bus-translation bridges that have limited FIFO’s, bridge disconnects, inefficient pre-fetching, and retires that result in latency and throughput penalties, CoSine supports multiple paths with concurrent access to its large Primary DDR array.  This provides seamless, transparent access between endpoints residing on different bus topologies and results in maximum total bandwidth.

Significant efforts have been applied to CoSine and CoSine based board-level products with regards distributing heavy signal loads, reducing transmission line reflections, signal routing, termination and bank interleaving, each of which becomes more challenging with larger amounts of memory.

The primary memory array uses 133MHz DDR SDRAM and can be configured with up to 8GB on the MM-333D ATCA board and 1GB per CoSine node on the VxS MM-15x0 and MM-16x0.  The multi-port controller uses 72-bit data with a 64-bit data bus and an additional 8-bits for error correction code that is generated on writes and verified on reads.

ECC
Error detection and correction, error logging and other diagnostic information are transmitted to the requesting interface for statistical gathering.  The error correction logic corrects single bit errors and detects double bit errors.  This requires that the minimum size write to the array be 64-bits (8-bytes), with an additional 8-bits (1-byte) for ECC code.