Quad FPGA VPX VITA 46 Carrier with two PMC/XMC sites and four Serial RapidIO ports on P1
 
 

 
Two CoSine 2VP70 System-on-Chips
Two V-4 LX160 CoSine Companion Devices
Two XMC/PMC sites
14 independent memory arrays with total bandwidth of over 40 GB/s
Four embedded PowerPC™ processors
Complete Serial RapidIO x4 connectivity
VITA 46 format
Rugged Air Cooled and Conduction Cooled versions

 
 

Description

MM-1650

The MM-1650  combines the industry’s most powerful System-on-Chip, CoSine™, with the application optimized architecture of an Othello® VME carrier.

Mezzanine Sites

Mezzanine sites on the MM-1650 can support either PMCs or XMCs. Configured for PMC support, each PCI bus can operate in 32-bit or 64-bit PCI 2.3 mode at up to 66MHz or in 64-bit PCI-X mode at up to 133MHz. Configured for XMCs, the sites can support the Aurora™ protocol with four MGTs or Serial RapidIO x4.

Backplane Connectivity

In addition to having a VME320 2eSST interface, the MM-1650 is the first VME board to include complete on-board Serial RapidIO switch fabric connectivity, with four independent Serial RapidIO ports to the VITA 46 P1 MGT backplane connector per the VITA 46.3 draft standard.

LX160 and V-4 Logic Slices

The MM-1650 is the first VME board to include the V-4™ LX™ series of FPGAs from Xilinx®. The LX device is notable in the large amount of FPGA slices that it provides for logic intensive implementations (see Xilinx V-4 Family Overview).

It can sometimes be difficult to predict logic resource utilization requirements in advance of RTL implementation. The LX family addresses this concern by offering massive logic densities. In the Xilinx V-4 portfolio, the LX160 is second in size only to the LX200. It offers over 67,000 FPGA slices for logic-centric applications requiring maximum gate count.

While using RTL abstraction tools such as The MathWork’s Simulink and Xilinx System Generator can reduce FPGA development time, resulting compiled VHDL can be verbose and require many more slices than might otherwise be required from hand coded state machines. The LX160 counters this concern by providing a large platform that provides the equivalent of approximately 15 million ASIC gates.

CoSine Compute Nodes

The MM-1650 contains two independent CoSine Compute Nodes (CCNs). A single CCN is comprised of a CoSine Primary Device (V-II Pro™ 2VP70™), a CoSine Companion Device (V-4 LX160) – see CoSine and CoSine Companion Device Configurations – and the following:

  • Two embedded PowerPC 405GP processors

  • One multi-ported primary DDR array, up to 1GB, for seamless bus translation between the mezzanine port and crossbar port to the backplane

  • Two dedicated 128MB DDR arrays local to each PowerPC processor

  • Four independent 9MB QDR II SRAM arrays local to the LX160 for FPGA processing operations

  • FPGA Platform Flash

Aggregate memory bandwidth exceeds 20GB/s per CCN, providing a total of over 40 GB/s on the MM-1650.

PowerPC Processors and Infrastructure

Each of the two embedded PowerPCs in each 2VP70 is a fully functional computer, each with its own DDR array, programmable Flash, UART, and shared Ethernet. Processors can host device drivers, perform message passing, service interrupts, or execute floating point operations. Each processor includes a complete BSP with all internal SoC device drivers fully integrated so customers can download application files “out of the box”.

Reconfigurable Processing

Each of the LX160s have additional FPGA platform Flash to store multiple bitstreams. Because the principal System-on-Chip functionality is largely contained in the 2VP70 CoSine Primary Device, the MM-1650 is optimally designed for reconfigurable processing. This approach enables the LX160 CoSine Companion Devices, which contain User Programmable Logic, to be reconfigured by the 2VP70 CoSine Primary Devices without the 2VP70s needing to reconfigure themselves.

Temperature Sensing

The MM-1650 contains a CPLD that monitors the temperatures of the CoSine Primary Devices, CoSine Companion Devices, and primary circuit board to ensure proper operation. Status updates can be received by the CoSine PowerPC processors that can then make intelligent decisions, display status to user programmable LEDs, or communicate information over its Ethernet link to remote destinations.

Debug Ports

Debug ports include four RS-232 UART consoles, one board/system push button reset switch, and two processor JTAG debug ports. Debug ports are available out the front panel or backplane via P0.

Ruggedized Options

The MM-1650DR is a rugged, extended temperature air cooled board with an operating temperature of -40°C to +71°C. The MM-1650DTF is a rugged conduction cooled board with an operating temperature of -40°C to +85°C with cabling out the front panel, and the MM-1650DTB is a rugged conduction cooled board with an operating temperature of -40°C to +85°C with cabling onto the backplane. Both the MM-1650DR, MM-1650DTF, and MM-1650DTB were designed for optimal heat dissipation and deployment in environments that undergo severe shock and vibration.

MM-1650 Spec Sheet.pdf