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MM-6260AD
A 128MB,
High-Density, VMEbus DRAM Memory Module |
| Features |
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Capacity 16,
32, 64, 128M |
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Cycle
Time/Access Time (nsec)
Block Transfer-BLT, Page Mode Read:
120/90, Write: 120/50
Non Block Transfer, CACHE Hits Read:
175/135, Write: 175/70 |
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Parity
generation and checking on each byte |
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Block
transfers (BLT) 256 bytes sequential
access,
expandable to 64KB (jumper-selectable |
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Module
Selection on 1MB boundaries, with
switch-selectable lower and upper
limits |
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Lifetime
Warranty on parts and labor |
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Read/Write
Access 175 nsec/50 nsec (Fast Write) |
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VMEbus-compatible per Rev C1 A32/A24,
D32/D16/D8 (UAT) |
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Description |
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 MM-6260AD Product
Specification Sheet (PDF file format)
There is no description for this item right
now. |
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MM-260AD
Specifications |
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Capacity
: 16M, 32M, 64M, 128MB |
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Cycle/Access Time (nsec)
:
Read: 120/90, Write: 120/50 (BLT, Page Mode)
Read: 175/135, Write: 175/70 (CACHE Hits, No
BLT) |
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Address
: A32/A24 address bits |
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Data In/Data Out
: D32/D16/D8 |
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Sequential Access
: Block Transfer within 256 byte boundary
(BLT), expandable to 256KB |
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Address Modifiers
: 6-bit, decoded by socketed IFL with the
following codes:
A24: 39, 3A, 3D and 3E
A32: 09, 0A, 0D and 0E
A24 with BLT: 38, 3F
A32 with BLT: 0B, 0F |
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Parity
: Byte-wide parity generation and checking;
parity output stored and transmitted via
BERR* |
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Interface
: VMEbus-compatible per Rev C.1 |
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Modes of Operation
: Read, write, read-modify-write, Page Mode
in BLT, and refresh |
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Refresh
: Hidden refresh, 200 nsec every 15 usec |
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Memory Selection
: 1MB boundaries, switch-selectable for the
upper and lower limits |
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Operating Temperature
: 0 to 60°C |
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Storage Temperature
: -40 to +85°C |
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Relative Humidity
: Up to 95% without condensation |
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Power Requirements
: +5V (Fully-populated), Operate 2.8A (max.)
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