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MM-6326AD
A 64MB,
Dual Port, VME/VSB Compatible DRAM Memory |
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Capacity: 8, 16, 32, 64M |
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Cycle Time/Access Time (nsec) Read
125/75, Write 125/50 (Block
Transfer-BLT, Page Mode and
Bank-Interleave) |
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Compatible with VMEbus Rev C1 and
VSBbus Rev C with A32/A24/D16/D8 (UAT)
for VME and A32/D32 for VSB |
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Block Transfer for sequential access
for both ports |
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Module Selection on 1MB boundaries,
jumper-selectable for lower and upper
limits on each bus |
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VMEbus Control Status Register (CSR)
for parity reporting and control |
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Write-Wrong Parity for diagnostics |
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Parity generation and checking for
error detection on each byte |
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Lifetime Warranty |
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Description |
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 MM-6326AD Product
Specification Sheet (PDF file format)
The MM-6326AD is a high speed, dual-port, single
card slot memory module that provides up to 64MB for
VME/VSB systems. It is intended for high performance
applications employing Bank-Interleave, Page Mode
and Block Transfer at data rates greater than
30MB/sec. It also supports sequential access (BLT)
of 256 bytes on the VME and 64KB on the VSB bus.
The MM-6326AD is compatible with MVME130/131,
MVME135/136, MVME141 and Delta Series systems.
The Control Status Register (CSR), located in the
short I/O address space, stores and reads byte-wide
parity errors detected on the VME/VSB buses. The
other bits enable Write-Wrong parity for
diagnostics, disable VME-port and determine whether
the memory is CACHEable on the VSB bus. Parity
generation and checking are provided for each byte;
parity status is stored and transmitted via BERR*.
Reliability is ensured by burn-in and running memory
diagnostics that check operation for 48 hours while
temperature-cycling boards from 0 to 60°C. Also,
reliability is backed up by Micro Memory, LLC's
Lifetime Warranty.
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MM-5410D
Specifications |
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Capacity
: 8MB, 16MB, 32MB, 64MB |
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Cycle/Access Time (nsec)
: Read: 125/75, Write: 125/50 (Block
Transfer-BLT, Page Mode and
Bank-Interleave), Read: 200/150, Write:
200/90 (Bank-Interleave) |
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Address
: 32 bits for VMEbus, 32 bits
multiplexed with 32 data bits for the VSB
bus |
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Data In/Data Out
: 8, 16, 32 bits (UAT) for VMEbus, 32
bits for VSB bus |
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Sequential Access
: Block Transfer (BLT) of 256 bytes on
VMEbus
64KB on VSB bus |
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Address Modifiers
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AM0-AM5 are decoded by socketed IFL with the
following codes:
A24: 39, 3A, 3D and 3E
A32: 09, 0A, 0D and 0E
A24 with BLT: 38, 3F
A32 with BLT: 0B, 0F |
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Parity Checking
: Byte-wide parity generation and checking;
parity output stored and transmitted via
CSR; Write-Wrong parity for diagnostics |
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Control Status Register
(CSR) :
Read/Write, 8 bits wide, jumper-selectable,
occupies one location in VME I/O space (A16) |
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CSR Format
:
D0 Enable Parity Out
D1 Write-Wrong Parity
D2 Memory CACHEable for VSB
D6 VMEbus Disable
D7 Parity Error
Others: Don't Care |
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Interface
: VME Rev C1 and VSB Rev C |
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Modes of Operation
: Read, write, read-modify-write, Page Mode
in BLT, and refresh |
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Memory Selection
: Two independent memory banks,
jumper-selectable on 1MB (100000H)
boundaries for each port by setting the
upper and lower limits |
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Operating Temperature
: 0 to +60°C |
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Storage Temperature
: -40 to +85°C |
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Relative Humidity
: Up to 95% without condensation |
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Power Requirements
: 5V at 5.5A |
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